/*
 * padl_gpio.h
 *
 *  Created on: 17/02/2010
 *      Author: gustavo
 */

#ifndef PADL_GPIO_H_
#define PADL_GPIO_H_

#include "target.h"


#define padl_gpio_OldGPIO0 		((padl_gpio_OldGPIOType *)0xE0028000 + 0x00000)
#define padl_gpio_OldGPIO1 		((padl_gpio_OldGPIOType *)0xE0028000 + 0x00010)

#define padl_gpio_GPIOInterrupt	((padl_gpio_GPIOInterruptType *)0xE0028080)

#define padl_gpio_GPIO0        	((padl_gpio_GPIOType *)(0x3FFFC000 + 0x00000))
#define padl_gpio_GPIO1        	((padl_gpio_GPIOType *)(0x3FFFC000 + 0x00020))
#define padl_gpio_GPIO2        	((padl_gpio_GPIOType *)(0x3FFFC000 + 0x00040))
#define padl_gpio_GPIO3        	((padl_gpio_GPIOType *)(0x3FFFC000 + 0x00060))
#define padl_gpio_GPIO4        	((padl_gpio_GPIOType *)(0x3FFFC000 + 0x00080))


typedef struct {
	REGISTER RW U32 IOPIN0;
	REGISTER RW U32 IOSET0;
	REGISTER RW U32 IODIR0;
	REGISTER WO U32 IOCLR0;
} padl_gpio_OldGPIOType;

typedef struct {
	union {
		REGISTER RO U32 IO_INT_STAT;
		struct {
			REGISTER RO BOOL P0Int : 1;
			U32 : 1;
			REGISTER RO BOOL P2Int : 1;
			U32 : 29;
		} IO_INT_STAT_detailed;
	};
	REGISTER RO U32 IO0IntStatR;
	REGISTER RO U32 IO0IntStatF;
	REGISTER WO U32 IO0IntClr;
	REGISTER RW U32 IO0IntEnR;
	REGISTER RW U32 IO0IntEnF;
	U32 RESERVED0[3];
	REGISTER RO U32 IO2IntStatR;
	REGISTER RO U32 IO2IntStatF;
	REGISTER WO U32 IO2IntClr;
	REGISTER RW U32 IO2IntEnR;
	REGISTER RW U32 IO2IntEnF;
} padl_gpio_GPIOInterruptType;

typedef struct
{
	union {
		REGISTER RW U32 FIODIR;
		struct {
			REGISTER RW U16 FIODIRL;
			REGISTER RW U16 FIODIRH;
		};
		struct {
			REGISTER RW U8 FIODIR0;
			REGISTER RW U8 FIODIR1;
			REGISTER RW U8 FIODIR2;
			REGISTER RW U8 FIODIR3;
		};
	};
	U32 RESERVED0[3];
	union {
		REGISTER RW U32 FIOMASK;
		struct {
			REGISTER RW U16 FIOMASKL;
			REGISTER RW U16 FIOMASKH;
		};
		struct {
			REGISTER RW U8 FIOMASK0;
			REGISTER RW U8 FIOMASK1;
			REGISTER RW U8 FIOMASK2;
			REGISTER RW U8 FIOMASK3;
		};
	};
	union {
		REGISTER RW U32 FIOPIN;
		struct {
			REGISTER RW U16 FIOPINL;
			REGISTER RW U16 FIOPINH;
		};
		struct {
			REGISTER RW U8 FIOPIN0;
			REGISTER RW U8 FIOPIN1;
			REGISTER RW U8 FIOPIN2;
			REGISTER RW U8 FIOPIN3;
		};
	};
	union {
		REGISTER RW U32 FIOSET;
		struct {
			REGISTER RW U16 FIOSETL;
			REGISTER RW U16 FIOSETH;
		};
		struct {
			REGISTER RW U8 FIOSET0;
			REGISTER RW U8 FIOSET1;
			REGISTER RW U8 FIOSET2;
			REGISTER RW U8 FIOSET3;
		};
	};
	union {
		REGISTER WO U32 FIOCLR;
		struct {
			REGISTER WO U16 FIOCLRL;
			REGISTER WO U16 FIOCLRH;
		};
		struct {
			REGISTER WO U8 FIOCLR0;
			REGISTER WO U8 FIOCLR1;
			REGISTER WO U8 FIOCLR2;
			REGISTER WO U8 FIOCLR3;
		};
	};
} padl_gpio_GPIOType;

#endif /* PADL_GPIO_H_ */
